JTAG

JTAG (Joint Test Action Group) is a standard dedicated to electronics system automated testing.
It allows to test all chips that have JTAG functionality with a single test connector. To allow this, all JTAG devices are daisy chained like on the picture below. In reality, there is often one JTAG connector per device because debug tools do not always support chain.

Signals

Following signals are used for JTAG :

  • TMS, (Test Mode Select) Signal to enable JTAG communication
  • TCK, (Test ClocK) Clock signal
  • TDI, (Test Data Input) Data Input
  • TDO, (Test Data Output) Data Output
  • TRST, (Test ReSeT) Optional, allows to reset JTAG Controller, Active low


Following signals are optionals :

  • RTCK, (Returned Test Clock) Optional signal, allows to adjust JTAG clock depending on the target
  • NRST, (“Neutral Test Reset) Target reset, often connected to System reset

Connectors

Multiple connectors versions exists depending on debug tools. Most commons are the following

ARM 20 pins

Signal Pin# Pin# Signal
VREF 1 2VSUPPLY
nTRST 3 4GND
TDI 5 6GND
TMS 7 8GND
TCK 910GND
RTCK 1112GND
TDO 1314GND
nSRST 1516GND
DBGRQ 1718GND
DGBACK1920GND

ARM 14 pins

Signal Pin# Pin# Signal
VREF 1 2GND
nTRST 3 4GND
TDI 5 6GND
TMS 7 8GND
TCK 910GND
TDO 1112nSRST
VREF 1314GND

MIPS EJTAG

Signal Pin# Pin# Signal
nTRST 1 2GND
TDI 3 4GND
TDO 5 6GND
TMS 7 8GND
TCK 910GND
nSRST 1112NC
DINT 1314VREF

Altera Byteblaster 10 pins

Signal Pin# Pin# Signal
TCK 1 2GND
TDO 3 4VREF
TMS 5 6NC
NC 7 8NC
TDI 910GND

AVR 10 pins

Signal Pin# Pin# Signal
TCK 1 2GND
TDO 3 4VREF
TMS 5 6nSRST
NC 7 8nTRST
TDI 910GND
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