PCB Layout


  • 5 mm without chips on all PCB edges
  • Decoupling capacitors vias are routed as follow
  • Bulk capacitors : 22uF every square inch per power plane
  • Decoupling capacitors : 1x100nF per power ball
  • Power planes are as large as possible
  • Analog power planes are as large as possible


  • PCB revision shall be indicated
  • PCB reference shall be indicated


  • Silkscreen sign shall indicate connector Pin#1
  • A text shall indicate connector function
  • All connectors even debug shall be easy to access
  • A line shows connector outline
  • Check that location reference is indicated as on the schematics
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