PCB Layout

Footprint

BGA

IPC-7351A for NSMD Pads

Nominal Ball Diameter Reduction Land Pattern Density Level Nominal Land Diameter Land Variation
0.7525%A0.550.60-0.50
0.6525%A0.500.55-0.45
0.625%A0.450.50-0.40
0.5525%A0.400.45-0.35
0.520%B0.400.45-0.35
0.4520%B0.350.40-0.30
0.420%B0.300.35-0.25
0.3520%B0.300.35-0.25
0.320%B0.250.25-0.20
0.2520%B0.200.20-0.17
0.215%C0.170.20-0.14
0.1715%C0.150.18-0.12
0.1515%C0.130.15-0.10

Placement

Place CPU and DDR chips on the same side of PCB to minimize the number of Vias. It is preferred to place CPU and DDR chips over ground plane.

Routing

Route signals in this order :

  1. Data signals (DQ[0:xx], DM[x], DQS/DQSn pairs). Data signals must be routed without any via.
  2. Clock signals (CLK,CLKn). Clock signals must be routed without any via.
  3. Address control signals on top and bottom layers

To check skew between signals, internal delay from CPU or package must be taken in account.

During layout checking some signals can have minimal skews like Clock to DQS.

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